Method of producing isolated regions for an integrated circuit s

Metal working – Method of mechanical manufacture – Assembling or joining

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

29576E, 29578, 29580, 148175, 148DIG26, 148DIG85, 156643, 156662, 357 49, 357 50, H01L 2176, H01L 2195

Patent

active

045703302

ABSTRACT:
Grooves are formed in a single crystal silicon wafer in a pattern to encircle surface areas. Silicon dioxide is placed in the grooves and on the surface and then removed from certain of the areas. Layers of silicon are epitaxially grown only on these areas and their surfaces are oxidized. Polycrystalline silicon is deposited to a thickness greater than that of the epitaxial layers. Both sides of the wafer are ground and polished to produce flat, planar, opposite surfaces; one surface exposing surface areas of the epitaxial layers, the other surface exposing the silicon dioxide in the grooves. The resulting substrate has two types of silicon sections, each of which is electrically isolated from the other by silicon dioxide partitions. One type of section is of silicon of the original wafer, has a surface area in only one surface, and is suitable for the fabrication of low voltage, low power devices therein. The other type of section has two zones, one of silicon of the original wafer at one surface and the other of epitaxial silicon at the other surface. This type of section is suitable for the fabrication of high voltage, high power devices therein.

REFERENCES:
patent: 3461003 (1969-08-01), Jackson
patent: 3850707 (1974-11-01), Bestland
patent: 3884733 (1975-05-01), Bean
patent: 3905037 (1975-09-01), Bean et al.
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4255209 (1981-03-01), Morcom et al.
patent: 4393573 (1983-07-01), Kato et al.
patent: 4393574 (1983-07-01), Shimbo
patent: 4481707 (1984-11-01), Cunniff
patent: 4507158 (1985-03-01), Kamins et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of producing isolated regions for an integrated circuit s does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of producing isolated regions for an integrated circuit s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of producing isolated regions for an integrated circuit s will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1543255

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.