Patent
1996-06-11
1998-04-28
Butler, Dennis M.
395553, 395558, G06F 104
Patent
active
057457409
ABSTRACT:
A technique for making it possible to complete, within a shorted period of time, clock tuning processing which is performed for constituent units in a parallel processing computer system. In each of the constituent units, a tuning scan loop is formed by continuously connecting together a plurality of clock tuning latches. A non-volatile memory is provided for previously storing clock tuning data inherent to each constituent unit. A plurality of constituent units which are to be subjected to clock tuning processing are simultaneously designated by a service processor. In each designated constituent unit, the clock tuning data stored in the non-volatile memory are successively sent and written into the respective clock tuning latches.
REFERENCES:
patent: 4714924 (1987-12-01), Ketzler
patent: 5235566 (1993-08-01), Merrill
patent: 5455931 (1995-10-01), Camporese et al.
Abstracts of Japan, 06-250982, Laid-Open Date, Sep. 9, 1994, I. Horiba, et al., Phase Locked Loop for Plural Processor.
Butler Dennis M.
Fujitsu Limited
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