Apparatus and methods for implementing dedicated cache flushing

Details Apparatus and methods for implementing dedicated cache flushing Apparatus and methods for implementing dedicated cache flushing

1996-05-28

1998-04-28

Swann, Tod R.

395471, 395473, 395468, G06F 1212

Patent

active

057457301

ABSTRACT:
A bus interface is connected to a system bus for monitoring a bus command indicating that data is updated on a cache memory of a processor. If the data is updated on the cache memory, the external tag storage device stores state information to indicate the update of the data and a physical address corresponding to the updated data. An external tag reading device reads the state information stored in the external tag storage device, when the updated data on the cache memory is stored in a main memory. A bus command for flushing the updated data from the cache memory to the main memory is generated, based on the state of the tag read out from the external tag storage device. An invalid bus command generation device outputs an invalid bus command to the system bus through a FIFO.

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patent: 5375216 (1994-12-01), Moyer et al.
patent: 5414827 (1995-05-01), Lin
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patent: 5553264 (1996-09-01), Ozverem et al.
patent: 5636374 (1997-06-01), Rodgers et al.

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