Method of making flash EEPROM or merged FAMOS cell without align

Details Method of making flash EEPROM or merged FAMOS cell without align Method of making flash EEPROM or merged FAMOS cell without align

1992-03-12

1993-12-28

Thomas, Tom

Fishing, trapping, and vermin destroying

437 43, 437 48, H01L 2170

Patent

active

052739260

ABSTRACT:
An electrically-erasable and programmable read-only memory cell includes a gate insulator layer formed on the face of a semiconductor layer having a first conductivity type. A conductive floating gate is formed on the gate insulator layer and has first and second portions with a gap substantially laterally separating the first and second portions. An interlevel insulator layer is formed on exposed faces of the floating gate. A conductive control gate is formed on the interlevel insulator layer in the gap and to be capacitively coupled to the floating gate. A source region and a drain region of a second conductivity type are formed beside opposite exterior lateral margins of the floating gate. The EEPROM cell of the invention avoids channel length alignment problems found in prior art EEPROM cells.

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