Semiconductor memory device and method for controlling an output

Details Semiconductor memory device and method for controlling an output Semiconductor memory device and method for controlling an output

1992-05-13

1994-03-15

Gossage, Glenn

Static information storage and retrieval

Addressing

Sync/clocking

36518905, G11C 702, G11C 1134

Patent

active

052951170

ABSTRACT:
When data read out from a memory cell array is output to an external device through an output buffer, a first and a second address transition detector generate a first read control pulse signal and a second read control pulse signal in response to a change in an address signal. An operation for reading out data is controlled using the first and second read control pulse signals, such that when noise generated by a change in power source potential, due to a change in output, causes a possible detected change in the address signal, the first and second address transition detectors control the output buffer so erroneous operation is prevented.

REFERENCES:
patent: 4272832 (1981-06-01), Ito
patent: 4480321 (1984-10-01), Aoyama
patent: 4573147 (1986-02-01), Aoyama et al.
patent: 4707809 (1987-11-01), Ando
patent: 4947374 (1990-08-01), Wada et al.

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