Semiconductor integrated circuit device having multi-contact wir

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

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257369, 257758, 257389, H01L 2966

Patent

active

054061008

ABSTRACT:
A semiconductor integrated circuit device comprises a complementary inverter implemented by a series combination of a p-channel enhancement type switching transistor and an n-channel enhancement type switching transistor, and a multi-level wiring structure coupled between the drain nodes of the two switching transistors and a capacitive load, wherein the multi-level wiring structure comprises a lower level wiring strip coupled at both ends thereof with the drain nodes through two sets of contact holes, and an upper level wiring strip coupled at both ends thereof with the lower level wiring strip through two contact holes so that both charge and discharge currents bi-directionally flow the upper and lower wiring strips, thereby enhancing the resistance against electro-migration.

REFERENCES:
patent: 5124778 (1992-06-01), Adachi
patent: 5182621 (1993-01-01), Hinooka
R. Eesley et al., "ACAP--A System for the Interactive Graphical Capture of Module Generators", IEEE 1991 Custom Integrated Circuits Conference, pp. 21.1.1-22.1.4, 1991.

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