Error detection scheme for ARQ systems

Details Error detection scheme for ARQ systems Error detection scheme for ARQ systems

1996-09-27

1998-04-28

Baker, Stephen M.

Excavating

371 3706, 371 379, 371 41, 371 682, H03M 1300, H04L 102, H04L 108, H04L 118

Patent

active

057455023

ABSTRACT:
A method of error correction for an ARQ system allows decoding when an even number of flawed packets are received. Multiple flawed replications of a transmitted bit sequence are compared bit-by-bit. A set of composite packets is formed containing all possible combinations of values at the disputed bit positions. A validity check is performed on each of the composite packets. If only a single composite packet passes the validity check, an acknowledgment signal is sent.

REFERENCES:
patent: 5241548 (1993-08-01), Dillon et al.
patent: 5497382 (1996-03-01), Levine et al.
patent: 5577053 (1996-11-01), Dent
patent: 5687188 (1997-11-01), Feeney et al.

Affiliated with

Also associated with

Rating

Error detection scheme for ARQ systems does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error detection scheme for ARQ systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error detection scheme for ARQ systems will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1540129