Method for forming a metal silicide interconnect in an integrate

Details Method for forming a metal silicide interconnect in an integrate Method for forming a metal silicide interconnect in an integrate

1994-03-29

1995-04-11

Quach, T. N.

Fishing, trapping, and vermin destroying

437 41, 437195, 437203, 437228, 448DIG19, 448DIG147, H01L 21283, H01L 21336

Patent

active

054058066

ABSTRACT:
A metal silicide interconnect (48, 92, 124) is formed in an integrated circuit using a sacrificial layer (30, 78, 108). In one embodiment a sacrificial layer of titanium nitride (30) is formed overlying a semiconductor substrate (12) and a polysilicon conductive member (20). The sacrificial titanium nitride layer (30) is then patterned and an underlying portion (40) of the semiconductor substrate (12), and a sidewall portion (42) of the polysilicon conductive member (20) are subsequently exposed. A metal layer (46) is deposited and then reacted with the exposed portion 40 of the semiconductor substrate (12) and the exposed sidewall (42) of the polysilicon conductive member (20) to form a metal silicide interconnect (48). The remaining portion of the sacrificial titanium nitride layer (38) is then removed after the metal silicide interconnect (48) has been formed without substantially altering the metal silicide interconnect (48).

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Pfiester et al., "An Integrated 0.5um CMOS Disposable TiN LDD/Salicide Spacer Technology," Proceedings of the International Electron Devices Meeting, Dec. 1989, pp. 781-784.

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