Pipelined architecture for patterned halftone generation

Details Pipelined architecture for patterned halftone generation Pipelined architecture for patterned halftone generation

1996-12-20

1998-04-28

Frahm, Eric

Facsimile and static presentation processing

Facsimile

Recording apparatus

358456, 358460, 382303, 382304, H04N 140, G06K 954

Patent

active

057452490

ABSTRACT:
The present invention is a super-scalar method and apparatus for the generation of halftone dot patterns in an image processing system. The super-scalar design employs at least one block of memory for the storage of at least one predetermined halftone dot pattern across a plurality of unique locations therein, and a sequencer for producing an index into said memory as a function of the position of the pixel along a scan line and the halftone dot characteristics. Also included is addressing circuitry for memory access control, to combine the index produced by said sequencer and a pixel value for the pixel to produce a memory address, the memory address being thereby employed to access one of said locations in memory and to cause said memory to output a signal representative of a portion of the halftone dot pattern stored at the unique addressed location.

REFERENCES:
patent: 4149194 (1979-04-01), Holladay
patent: 4185304 (1980-01-01), Halladay
patent: 4817175 (1989-03-01), Tenenbaum et al.
patent: 4918622 (1990-04-01), Granger et al.
patent: 5493419 (1996-02-01), Jadoin et al.

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