Scan-based delay tests having enhanced test vector pattern gener

Details Scan-based delay tests having enhanced test vector pattern gener Scan-based delay tests having enhanced test vector pattern gener

1994-07-20

1997-06-24

Beausoliel, Jr., Robert W.

Excavating

371 221, 371 225, 364717, G01R 3128

Patent

active

056423624

ABSTRACT:
This invention teaches circuitry and methods for performing delay tests, including skewed-load, broad-side, and STUMPS-related tests. More particularly a logic circuit (10), such as an integrated circuit, includes at least one block of combinational logic (12) having a plurality of input nodes and at least one output node. The logic circuit further includes delay test circuitry (14, 16, 18) that is coupled to the plurality of input nodes and to the at least one output node. The delay test circuitry has a scan-chain register (14) having a plurality of outputs coupled to the plurality of input nodes for establishing at least first and second multi-bit test vectors at the plurality of input nodes. The delay test circuitry further includes a plurality of XOR gates that are coupled to the scan-chain register. The plurality of XOR gates have outputs for establishing logic states of bits of the second test vector at the plurality of input nodes. In the skewed-load test the XOR gates overcome the one bit shift dependency problem, while in the broad-side and STUMPS test the XOR gates, in combination with one or more sources of random logic states, are used to introduce second vectors having optimal probabilities for launching transitions.

REFERENCES:
patent: 4503537 (1985-03-01), McAnney
patent: 4680539 (1987-07-01), Tsai
patent: 4687988 (1987-08-01), Eichelberger et al.
patent: 4688223 (1987-08-01), Motika et al.
patent: 4698830 (1987-10-01), Barzilai et al.
patent: 4745355 (1988-05-01), Eichelberger et al.
patent: 4801870 (1989-01-01), Eichelberger et al.
patent: 4855669 (1989-08-01), Mahoney
patent: 4912395 (1990-03-01), Sato et al.
patent: 4959832 (1990-09-01), Bardell
patent: 5042034 (1991-08-01), Correale, Jr. et al.
patent: 5130988 (1992-07-01), Wilcox et al.
patent: 5150366 (1992-09-01), Bardell, Jr. et al.
patent: 5278842 (1994-01-01), Berry et al.
patent: 5297151 (1994-03-01), Gruetzner et al.
patent: 5323400 (1994-06-01), Agarwal et al.
"Scan-Based Transition Test", by Jacob Savir and Srinivas Patil, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 8, Aug. 1993, pp. 1232-1241.
"On broad-side delay test", by J. Savir and S. Patil, Proc. 1994 VLSI Test Symposium, pp. 284-290, Apr. 1994.
"Built In Test For VSLI: pseudorandom techniques", John Wiley, 1987., pp. 285-289 by P. Bardell, W. McAnney, and the J. Savir.

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