Bus apparatus having hold registers for parallel processing in a

Details Bus apparatus having hold registers for parallel processing in a Bus apparatus having hold registers for parallel processing in a

1991-12-03

1993-04-20

Chan, Eddie P.

Boots, shoes, and leggings

364748, 364258, 3642582, 3642402, 36493546, 3649371, 3649374, 364DIG2, 395800, G06F 738

Patent

active

052048284

ABSTRACT:
In a microprocessor having a floating-point execution unit, a floating-point bus control apparatus for performing dual-operation instructions includes a multiplier unit having first and second multiplexed operand inputs, an adder unit also having first and second multiplexed operand inputs, a register for storing real and imaginary components of a constant, another register for storing an intermediate result of the multiplier unit and appropriate interconnections. The floating-point unit of the processor supplies first and second instruction source operands and a destination floating-point register. Multiplexers are used to select which operands are to be input to the appropriate operand inputs so as to implement the corresponding dual-operation algorithm.

REFERENCES:
patent: 4075704 (1978-02-01), O'Leary
patent: 4766564 (1988-08-01), DeGroot

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