Reduced RC delay between adjacent substrate wiring lines

Details Reduced RC delay between adjacent substrate wiring lines Reduced RC delay between adjacent substrate wiring lines

1996-09-30

1998-11-10

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257638, 438631, 438668, H01L 2900, H01L 2358

Patent

active

058359877

ABSTRACT:
A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon spheres define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are rigid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperatures up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are "T-topped" (i.e., viewed cross-sectionally). Dielectric fill is deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off an internal void.

REFERENCES:
patent: 3978269 (1976-08-01), Martin
patent: 4039480 (1977-08-01), Watson et al.
patent: 4450184 (1984-05-01), Longo et al.
patent: 4917857 (1990-04-01), Jaeckel et al.
patent: 5126192 (1992-06-01), Chellis et al.
patent: 5192715 (1993-03-01), Sliwa, Jr. et al.
patent: 5310700 (1994-05-01), Lien et al.
patent: 5407860 (1995-04-01), Stoltz et al.
patent: 5510645 (1996-04-01), Fitch et al.
patent: 5523615 (1996-06-01), Cho et al.
Ohkura et al. "A Novel Global Planarization Process Using Gap Filling With Self-Aligned Silica Spacer," VMIC Conference Jun. 27-29, 1995; 1995 ISMIC -104/95/0233.
Pawloski, "The Science and Engineering of Thermal Spray Coatings," p. 20, John Wiley and Sons.
Bulletin #ZPI-804 Insulating Bubbles Type IB-80 and IB-100; Jul. 1996.

Affiliated with

Also associated with

Rating

Reduced RC delay between adjacent substrate wiring lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduced RC delay between adjacent substrate wiring lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced RC delay between adjacent substrate wiring lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1529674