Circuit and method for performing equal duty cycle odd value clo

Details Circuit and method for performing equal duty cycle odd value clo Circuit and method for performing equal duty cycle odd value clo

1987-09-28

1989-02-21

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

377108, 328 55, 328 58, 3072721, H03K 2110, H03K 2370, H03K 2350

Patent

active

048072664

ABSTRACT:
A circuit for dividing a master clock by an odd integral value and producing a 50% duty cycle. A state machine develops set and clear signals which are of a timing proportion of n: n+1, where 2n+1 is the divisor value. The set signal is provided to one input of a bistable multivibrator or S-R latch to set the multivibrator to a given state, while the clear signal is combined with the master clock signal to delay or disable the clearing of the multivibrator by 1/2 count of the master clock, so that an n+1/2: n+1/2 proportion output clock signal is developed. Additionally, the circuit includes a state machine which determines which of a series of differing frequency master clock signals is active and when an external triggering event occurs so that the following rising edge of the output clock signal is delayed until a determined time after the triggering event to allow synchronization of the output clock signal.

REFERENCES:
patent: 3873815 (1975-05-01), Summers
patent: 3943379 (1976-03-01), McGriffin
patent: 4330751 (1982-05-01), Swain
patent: 4336394 (1982-12-01), Clendenning et al.
patent: 4560939 (1985-12-01), Dekarske et al.
patent: 4651103 (1987-03-01), Grimes
patent: 4656649 (1987-04-01), Takahashi
patent: 4703495 (1987-10-01), Bereznak
EDN, Divider Produces Symmetrical Output, Jan. 23, 1986, p. 212.
Traditional Approaches to Sequential Analysis and Design, Counters, pp. 386-405.
Compaq Computer Corp., Deskpro 386 Technical Reference Manual, pp. 2-33 and 2-34.
Compaq Computer Corp., Detailed Processor Descriptions, pp. 10 and 11 and relating to PAL design.

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