Process for producing a semiconductor memory device having memor

Details Process for producing a semiconductor memory device having memor Process for producing a semiconductor memory device having memor

1993-04-21

1994-03-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 60, 437 89, 437919, 148DIG14, H01L 2170

Patent

active

052926796

ABSTRACT:
A semiconductor memory device having an excellent data holding characteristics because of a small leak current from a trench and a process for producing the same are disclosed. An SiO.sub.2 film 12 having an appropriate pattern is formed on a P type silicon substrate 11. Trenches 14 are relatively formed on the SiO.sub.2 film 12 by selectively growing a P type epitaxial layer 13 on the silicon substrate 11 using the SiO.sub.2 film 12 as a mask. An N type layer 23 acting as an electrode of a capacitor 27 is formed on the inner wall of the trench 14 by the oblique ion implantation of impurities 22 thereto. A polycrystalline silicon film 25 acting as an opposite electrode of the capacitor 27 is formed on an ONO film 24 so that the ONO film 24 is disposed between the polysilicon film 25 and the SiO.sub.2 film. The semiconductor memory device which is produced by this method without etching to form the trenches 14 has a fewer crystal defects in the epitaxial layer 13 around the trenches 14. Accordingly, the data holding characteristics are improved since the leak current from the trenches 14 becomes less. As a result of this, higher density integration is possible since the device can be made with less capacitance of capacitors.

REFERENCES:
patent: 4843025 (1989-06-01), Morita
patent: 5026658 (1991-06-01), Fuse et al.
patent: 5106776 (1992-04-01), Shen et al.
patent: 5185282 (1993-02-01), Lee et al.
patent: 5236863 (1993-08-01), Irammanesh
Tsukamoto et al., "Double stacked capacitor with self-aligned poly source/drain transistor (DSP) cell for megabit DRAM", IEDM 1987, IEEE pp. 328-331.

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