Boots – shoes – and leggings
Patent
1985-12-16
1989-02-21
Lall, Parshotam S.
Boots, shoes, and leggings
364900, 364466, G06F 1300
Patent
active
048071412
ABSTRACT:
In a postage meter which includes a computer, a power supply for energizing the computer, a non-volatile memory for storing postage meter operating data, and wherein the computer includes a microprocessor adapted for processing the operating data, there is provided an improvement for protecting the operating data. The improvement comprises: the computer including (a) apparatus for detecting respective high level and low level output voltage signals from the power supply; (b) a first switching circuit operable in response to the detection of a high level output voltage signal for providing a power-up signal to the microprocessor and operable in response to the detection of a low level output voltage signal for providing a power-down signal to the microprocessor; (c) a second switching circuit operable in response to the detection of said high level signal for providing a not-reset signal to said microprocessor and operable in response to the detection of said low level signal for providing a reset signal to said microprocessor; and (d) apparatus for enabling operation of the non-volatile memory after the microprocessor has been provided with the power-up and not-reset signals, wherein the non-volatile memory enabling apparatus includes gate structure operable in response to timely receiving at least two respectively predetermined input signals for enabling the microprocessor to transfer said operating data between the microprocessor and the non-volatile memory, the non-volatile memory enabling apparatus includes a buffer circuit timely operable by the microprocessor for providing one of said two signals, and the microprocessor includes instrumentalities programmed for timely operating said buffer circuit and timely providing another of said two signals; and (e) third switching responsive to operation of the buffer circuit for inhibiting the operation of the second switching circuit to prevent the provision thereby of a reset signal to the microprocessor after the microprocessor is provided with a power-down signal and until the microprocessor has transferred the operating data from the microprocessor to the non-volatile memory.
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patent: 4253015 (1981-02-01), McFiggans et al.
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patent: 4323987 (1982-04-01), Holtz et al.
patent: 4445198 (1984-04-01), Eckert
patent: 4484307 (1984-11-01), Buatse
patent: 4534018 (1985-08-01), Eckert et al.
patent: 4547853 (1983-08-01), Eckert
patent: 4564922 (1986-01-01), Muller
DeSha Michael J.
Lall Parshotam S.
Pitchenik David E.
Pitney Bowes Inc.
Ramirez Ellis B.
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