Permutation memories

Boots – shoes – and leggings

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Details

307221D, 358138, 365 45, 365183, G11C 1140, G06G 719

Patent

active

041640233

ABSTRACT:
A permutation memory comprises an input control means for decoding, having plurality L of inputs for an L-bit binary number, and a plurality 2.sup.L of outputs. Means are connected to the decoding means, for initiating the read-in of the L-bit number. Means are provided for applying an input signal. A first plurality of 2.sup.L of normally open switching means are connected to the 2.sup.L outputs of the decoding means and to the signal applying means. A plurality of 2.sup.L of means are connected to the switching means, for storing a charge when a specific switching means, connected to a corresponding charge storing means, is in a closed condition. A second plurality 2.sup.L of switching means are connected to the first plurality of switching means and to the charge storing means. An output control means, connected to the second plurality of switching means, reads out the states of the 2.sup.L charge-storing means, as to the amount of charge in each. Means are connected to the read-out means, for initiating the read-out.

REFERENCES:
patent: 3909806 (1975-09-01), Uchida
patent: 3914748 (1975-10-01), Barton et al.
patent: 4007446 (1977-02-01), Elmer et al.
patent: 4092734 (1978-05-01), Collins et al.

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