Instruction issuing mechanism for processors with multiple funct

Details Instruction issuing mechanism for processors with multiple funct Instruction issuing mechanism for processors with multiple funct

1987-10-14

1989-02-21

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

048071153

ABSTRACT:
An instruction issuing mechanism for boosting throughput of processors with multiple functional units. A Dispatch Stack (DS) and a Precedence Count Memory (PCM) are employed which allow multiple instructions to be issued per machine cycle. Additionally, instructions do no have to be issued according to their order in the instruction stream, so that non-sequential instruction issuance occurs. In this system, multiple instruction issuance and non-sequential instruction issuance policies enhance the throughput of processors with multiple functional units.

REFERENCES:
patent: 3297999 (1967-01-01), Shimabukuro
patent: 3346851 (1967-10-01), Thornton
patent: 3462744 (1969-08-01), Tomasulo et al.
patent: 3718912 (1973-02-01), Hasbrouck et al.
patent: 3962706 (1976-06-01), Dennis
patent: 4050058 (1977-09-01), Garlic
patent: 4128880 (1978-12-01), Cray
patent: 4179734 (1979-12-01), O'Leary
patent: 4197589 (1980-04-01), Cornish
patent: 4466061 (1984-08-01), De Santis
R. M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal, Jan. 1967.
R. M. Keller, "Look-Ahead Processors", Computing Surveys, vol. 7, No. 4, Dec. 1975.
J. W. Bowra and H. C. Torng, "The Modeling and Design of Multiple Function-Unit Processors", IEEE Transactions on Computers, vol. C-25, No. 3, Mar. 1976.
Siewiorek, D. P. "Computer Structures: Principles and Examples", 1982, pp. 278, 288-292.
H. C. Torng et al., "An Instruction Issuing Approach to Enchancing Performance in Multiple Functional Units Processors", IEEE Transactions on Computers, vol. C-35, No. 9, Sep. 86.
J. E. Thornton, "Parallel Operation in the Control Data", A FIES Proceedings, vol. 26, pt. 2, 1964, pp. 489-496.
G. Bell et al., "The Cray-1 Computer System", Comm. of the ACM, vol. 21, No. 1, Jan. 1978.
V. P. Srinii and J. F. Asenjo, "Analysis of Cray-1S Architecture", ACM, 1983.

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