Method of making SRAM cell and structure with polycrystalline p-

Details Method of making SRAM cell and structure with polycrystalline p- Method of making SRAM cell and structure with polycrystalline p-

1991-06-03

1993-04-20

Thomas, Tom

Fishing, trapping, and vermin destroying

437 48, 437 52, 437 57, 437 60, 437200, 437918, H01L 2170

Patent

active

052042790

ABSTRACT:
A method for forming a SRAM structure with polycrystalline P-channel load devices of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A field oxide region is formed over a portion of the substrate. A first gate electrode of a first N-channel field effect device is formed over the substrate having a source/drain region in the substrate. A second gate electrode of a second N-channel field effect device is also formed over the substrate and a portion of the field oxide. A first insulating layer is formed over the integrated circuit containing an opening exposing a portion of the source/drain region and the second gate electrode of the first and second N-channel devices respectively. An interconnect layer having a doped polysilicon layer and a barrier layer is formed over the integrated circuit, patterned and etched to define a shared contact region covering the exposed source/drain region and the second gate electrode of the N-channel devices. A second insulating layer is formed over the integrated circuit having an opening exposing a portion of the interconnect layer. A first conductive layer is formed over the integrated circuit, patterned and etched to define a first and a second gate electrode of a first and a second P-channel field effect device respectively. A gate oxide layer is formed over a portion of the first gate electrode and a portion of the second gate electrode of the first and second P-channel devices. A second conductive layer is formed over the integrated circuit, patterned and etched to define a source/drain and channel region of the first gate electrode of the first P-channel device and covering a portion of the second gate electrode of the second P-channel device.

REFERENCES:
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patent: 4549340 (1985-10-01), Nagasawa et al.
patent: 4554729 (1985-11-01), Tanimura et al.
patent: 4676866 (1987-06-01), Tang et al.
patent: 4786612 (1988-11-01), Yau et al.
Ikeda et al; A Polysilicon Transistor Technology for Large Capacity SRAMs; Apr. 1990 in IEEE-IEDM 90-469 pp. 18. 1.1-4.
U.S. patent application Ser. No. 516,272, Apr. 30, 1990, Brady et al.
U.S. patent application Ser. No. 531,014, May 31, 1990, Chan et al.

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