Pattern-recognition systems having selectively alterable reject/

Communications: electrical – Digital comparator systems

Patent

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Details

3401463D, G06K 900

Patent

active

040328872

ABSTRACT:
Two independent recognition logics produce separate identifications of an input pattern. In a selectable mode for minimizing reject errors, any non-reject identification is gated out. In a mode for minimizing substitution errors, both identifications must be the same. Differing, non-reject identifications always cause a reject code to be gated out.

REFERENCES:
patent: 3641495 (1972-02-01), Kiji
patent: 3764978 (1973-10-01), Tyburski et al.
patent: 3764980 (1973-10-01), Dansac et al.
patent: 3832682 (1974-08-01), Brok et al.

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