Low overhead input and output boundary scan cells

Details Low overhead input and output boundary scan cells Low overhead input and output boundary scan cells

1997-07-24

1999-01-12

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058598600

ABSTRACT:
Input and output boundary scan cells respectively include latchable input and output buffers (103,40) which respectively utilize the input and output buffers of the integrated circuit in which the boundary scan cells are provided. The latchable input and output buffers provide the input and output boundary scan cells with a low overhead latching function.

REFERENCES:
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5134314 (1992-07-01), Wehrmacher
patent: 5206545 (1993-04-01), Huang
patent: 5459737 (1995-10-01), Andrews
Dilip K. Bhavsar,, "Chapter 17. Cell designs that Help Test Interconnect Shorts", IEEE, 1990, pp. 183-189.
Lee Whetsel, "IEEE STD. 1149.1--An Introduction", NEPCON, Feb. 1993, 10 pages.
David George, "Use a Reprogrammable Approach to Boundary Scan for FPGAs", EDN-Design Feature, Aug. 5, 1993.
Nai-Chi, Lee, "A Hierarchical Analog Test Bus Framework for Testing Mixed-Signal Integrated Circuit and Printed Circuit Boards", Journal of Electronic Testing, 1993.

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