Data processing system having a CPU register file and a memory a

Details Data processing system having a CPU register file and a memory a Data processing system having a CPU register file and a memory a

1976-10-01

1979-01-02

Chapnick, Melvin B.

Boots, shoes, and leggings

G06F 1300

Patent

active

041330285

ABSTRACT:
A data processing system having a particular configuration of interconnecting data paths among the data handling units thereof. The central processor unit of the system includes a skew-protected quadriport register file having two read and two write input ports as well as a separately located instruction register and a separately located memory address register. The first read port is connected to one of a pair of inputs to an arithmetic-logic unit and the second read port is connected to the other one of the pair of inputs to the arithmetic-logic unit and to the first write port of the register file. The output of the arithmetic-logic unit is connected to the memory address register and to a shifter unit, the shifted output thereupon being connected to the second write port of the register file. The system uses two separate buses for transferring data between the central processor unit and memory units and between the central processor unit and external input/output devices. A separate memory address unit transfers addresses from the memory address register to the memory units.

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