Logic circuit having normal input/output data paths disabled whe

Details Logic circuit having normal input/output data paths disabled whe Logic circuit having normal input/output data paths disabled whe

1989-01-30

1991-12-31

Atkinson, Charles E.

Excavating

G01R 3128

Patent

active

050777408

ABSTRACT:
A logic circuit having a plurality of macrocells for processing test input data and outputting a result of the process. Each of the macrocells is tested independently of each other and includes an input-output circuit. The input-output circuit comprises: a first holding register for holding the test input data; a selector circuit for shutting off an input path for normal operation signals to the macrocell in question at the time of testing the macrocell, selecting the test input data held in the first holding register, and outputting the selected test input data to a logic circuit to be tested in the macrocell; a second holding register for holding test output data obtained as a result of a test process carried out in the macrocell based on the test input data, and outputting the test output data externally; and a switching circuit for shutting off, at the time of testing the macrocell, an output path for normal operation signals from the microcell to other portions of the logic circuit.

REFERENCES:
patent: 4503386 (1985-03-01), DasGupta et al.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4817093 (1989-03-01), Jacobs et al.
patent: 4897837 (1990-01-01), Ishihara et al.
patent: 4910734 (1990-03-01), Segawa et al.
Eichelberger et al., "A Logic Design Structure for LSI Testability", Proc. Design Automation Workshop 14th (1977), pp. 462-468.

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