Test mode enable scheme for memory

Details Test mode enable scheme for memory Test mode enable scheme for memory

1991-05-22

1991-12-31

Baker, Stephen M.

Excavating

371 211, 371 214, G01R 3128, G01R 3130, G11C 2900

Patent

active

050777386

ABSTRACT:
A test mode enable circuit in which a test mode code is written to one latch and a test mode enable code is written to a second latch. The test mode enable code is compared to preprogrammed values stored in the enable circuit. When the test mode enable code matches the preprogrammed value, a presence of a high voltage activates a test mode enable signal for entering the test mode. The latched test mode code is then used to perform the desired test. Additionally a pulsewidth detector is used as a filter to permit only high voltages of a minimum pulsewidth duration to activate the enable signal thereby preventing false triggering.

REFERENCES:
patent: 4689740 (1987-08-01), Moelands et al.
patent: 4701920 (1987-10-01), Resnick et al.
patent: 4710933 (1987-12-01), Powell et al.
patent: 4791358 (1988-12-01), Sauerwald et al.
patent: 4841233 (1989-06-01), Yoshida
patent: 4947378 (1990-08-01), Jinbo et al.
McAdams, H. et al., "Al-Mbit CMOS Dynamic RAM With Design-For Test Functions", IEEE Jour. of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 635-642.
Millman, J. et al., Microelectronics, McGraw-Hill, 1987, pp. 313-325.

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