Method and circuit for timing the reading of nonvolatile memorie

Details Method and circuit for timing the reading of nonvolatile memorie Method and circuit for timing the reading of nonvolatile memorie

1995-02-21

1996-07-02

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 36518901, G11C 700

Patent

active

055329721

ABSTRACT:
A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.

REFERENCES:
patent: 4827454 (1989-05-01), Okazaki
patent: 5432747 (1995-07-01), Fuller et al.
patent: 5463581 (1995-10-01), Koshikawa

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