Nonvolatile semiconductor memory having enhanced speed for erasi

Details Nonvolatile semiconductor memory having enhanced speed for erasi Nonvolatile semiconductor memory having enhanced speed for erasi

1994-12-13

1996-07-02

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518523, 36523003, 326105, G11C 800, G11C 1134

Patent

active

055329713

ABSTRACT:
An arrangement is provided to enhance the speed in the operation of erasing and programming of a nonvolatile semiconductor memory that is driven by a single supply voltage and to reduce the number of transistors making up the subword decoder circuit thereby minimizing the size of the device. For this purpose, in the subword decoder circuits WDi1-WDij that drive the word lines Wi1-Wij, the block selection address lines Bip and Bin generated from the first address line group are used as supply voltages for the inverter circuit that controls the voltage of the word line, and the gate selection address line Gj generated from the second address line group is used a gate input line.

REFERENCES:
patent: 5305279 (1994-08-01), Park et al.
patent: 5402386 (1995-03-01), Tavrow et al.
patent: 5412331 (1995-05-01), Jun et al.
patent: 5446700 (1995-08-01), Iwase

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