Floorplanning technique using multi-partitioning based on a part

Details Floorplanning technique using multi-partitioning based on a part Floorplanning technique using multi-partitioning based on a part

1995-04-03

1996-07-02

Teska, Kevin J.

Boots, shoes, and leggings

364490, 364491, H01L 2350

Patent

active

055329349

ABSTRACT:
A technique for integrated circuit floorplanning using irregularly shaped dies (e.g., triangular, elongated rectangular, parallelogram-shaped, etc.) is described whereby the layout of the integrated circuit die is accomplished by partitioning (slicing) the die into progressively smaller groups of more than two areas into which functions (active elements, or circuits) are assigned according to their area requirements. The die is iteratively sub-partitioned.

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