Microprogrammed microcomputer with high-speed interrupt for DRAM

Details Microprogrammed microcomputer with high-speed interrupt for DRAM Microprogrammed microcomputer with high-speed interrupt for DRAM

1994-05-25

1996-01-23

Powell, Mark R.

395550, 395494, G06F 932

Patent

active

054871573

ABSTRACT:
To speed up switch between the use of a data bus by CPU for reading and writing data and the use of the data bus for refreshing a DRAM in a microcomputer having a DRAM refresh function, a terminal count signal 20 which is activated by a refresh timer 9 when a memory subsystem 8 composed of an external DRAM needs to be refreshed is directly input into a microinstruction sequencer 15 for controlling the order of executing a set of microinstructions of CPU 2. Therefore, CPU 2 can interrupt the execution of a set of microinstructions to execute a refresh cycle and can resume the execution of the interrupted set of microinstructions as controlled by the microinstruction sequencer 15 after the refresh cycle is finished.

REFERENCES:
patent: 5379400 (1995-01-01), Barakat et al.
User's Manual, M33300GS-20 (M32/ASSP), pp. 38, 39.
Microprocessor, Nikkei Data Pro, Dec. 1990, PD70208(V40).

Affiliated with

Also associated with

Rating

Microprogrammed microcomputer with high-speed interrupt for DRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microprogrammed microcomputer with high-speed interrupt for DRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprogrammed microcomputer with high-speed interrupt for DRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1510866