Process for fabricating a stacked capacitor within a monolithic

Details Process for fabricating a stacked capacitor within a monolithic Process for fabricating a stacked capacitor within a monolithic

1991-04-30

1991-12-31

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 52, H01L 21266, H01L 2172

Patent

active

050772252

ABSTRACT:
A process for fabricating a stacked capacitor for use in monolithic integrated circuits using oxygen implantation. This invention provides a relatively simple process for manufacturing stacked capacitors having two series of interleaved plates. The process is unique, in that rather than requiring the use of a different material for each series of conductive plates, utilizes polycrystalline silicon for both series. The process proceeds with the deposition of alternating dielectric and polycrystalline silicon ("poly") layers, beginning and ending with a dielectric layer. Each poly layer is masked with photoresist, implanted with oxygen in unmasked regions, and then thermally annealed to convert all silicon in the unmasked regions into silicon dioxide. Each non-implanted poly region is horizontally offset from the non-implanted poly regions of the nearest superjacent and subjacent poly layers, which are, themselves, horizontally aligned. The resulting layer stack is masked and anisotropically etched, stopping on the bottom dielectric layer, to form a block of stacked layers, one vertical side of which comprises unoxidized edges of even numbered poly layers and oxidized edges of odd numbered poly layers, and a second vertical side of which comprises unoxidized edges of odd numbered poly layers and oxidized edges of even numbered poly layers. A tying layer is then blanket deposited over the block, masked and etched so that the unoxidized edges of even numbered poly layers are electrically connected by one a first typing layer remnant, while the oxidized edges of odd numbered poly layers are electrically connected by a second tying layer remnant.

REFERENCES:
patent: 4700457 (1987-10-01), Matsukawa

Affiliated with

Also associated with

Rating

Process for fabricating a stacked capacitor within a monolithic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating a stacked capacitor within a monolithic , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating a stacked capacitor within a monolithic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1509914