Self-diagnostic device for semiconductor memories

Details Self-diagnostic device for semiconductor memories Self-diagnostic device for semiconductor memories

Filed on

1995-10-19

Date issued

1996-10-01

Examiner

Beausoliel, Jr., Robert W.

Patent Class

Excavating

Other Related Categories

371 211, G11C 2900, G06F 1100

Type

Patent

Status

active

Patent number

055616712

Description

ABSTRACT:
A self-diagnostic device for checking the performance of memory matrix in semiconductor devices is presented. The device is applicable particularly to those IC testers having high bit and high capacity memories. The device is capable of performing march and checker tasks simultaneously. The program data contained in a CPU 1 are written into the memory matrix 5 by way of the data generation circuit 2 and the address generation circuit 3. The test data are entered into a comparator 4 at the timing governed by the clock generation circuit 6, and are compared with the expected data from the data generation circuit 2. When there is a non-coincidence, a defect signal is generated from a flip-flop (FF) circuit 9. In the present device, the conventional division circuits are replaced by two FF circuits 8, 9, and two EOR-gates 11, 12 and associated components to provide simplicity in circuit configuration and efficient operation while retaining the advantages offered by the conventional march- and checker-modes. The FF circuit 8 provides a set/reset-signal in response to a clock signal from the clock generation circuit 6. The EOR-gate 12 operates so as to generate an inverted signal of the lowermost bit A0 of either the output data from the FF circuit 8 or from the address generation circuit 3. The EOR-gate 11 generates inverted signals of the output data from the data generation circuit 2 upon receiving a signal from the EOR-gate 12.

REFERENCES:
patent: 4430735 (1984-02-01), Catiller
patent: 4672583 (1987-06-01), Hakaizumi
patent: 4788684 (1988-11-01), Kawaguchi et al.
patent: 4811294 (1989-03-01), Kobayashi et al.

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