Method of manufacture of multi-cell integrated circuit architect

Details Method of manufacture of multi-cell integrated circuit architect Method of manufacture of multi-cell integrated circuit architect

1993-10-12

1996-10-01

Ramirez, Ellis B.

Boots, shoes, and leggings

364489, 364491, G06F 1300

Patent

active

055616070

ABSTRACT:
A standard cell topography has a generally rectangular topography, circumscribed by a set of four mutually orthogonal cell boundary edges. Coupled in circuit with a standard AND gate circuit within the cell are a pair of sense nodes for testing the AND gate. The sense MOSFETs are adjacent to opposite cell edges and are connected to respective sense nodes. First and second parallel metallic control links, which are used to gate the sense MOSFETs, extend the width of the cell between opposing cell boundary edges, so as to facilitate placement of the cells in boundary edge-abutting relationship, so that abutting control links may effectively form continuous runs through all the cells of a respective row of cells. A first output terminal of the first sense MOSFET is adjacent to one boundary edge and a second output node of the second terminal of the second sense MOSFET is adjacent to the other opposing cell boundary edge. This edge proximity placement of the output nodes of the sense MOSFETs facilitates coupling of the MOSFET output nodes to boundary edge-located sense terminals, which intersect the cell boundary edges.

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