Method of fabricating a TFT with reduced channel length

Details Method of fabricating a TFT with reduced channel length Method of fabricating a TFT with reduced channel length

1995-06-02

1996-07-02

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 41, 437101, 437181, H01L 2128, H01L 2184

Patent

active

055321801

ABSTRACT:
A thin film transistor (TFT) having a reduced channel length and method of making same are disclosed for liquid crystal display (LCD) applications. The method of making the TFT includes the following process steps: (i) depositing and patterning the gate on a substrate; (ii) depositing and patterning an intrinsic a-Si layer, a n+ a-Si layer, and a source metal layer (e.g. Cr) over the gate; (iii) depositing and patterning an ITO layer to form a pixel electrode portion and a TFT source portion; (iv) etching the source metal layer so that it remains only under the ITO source portion so as to form the TFT source electrode; (v) depositing and patterning a metal (e.g. Mo) to form the drain of the TFT; and (vi) etching the n+ a-Si layer in the TFT channel area so that only the intrinsic semiconductor layer remains between the source and drain. The resulting TFT has a reduced channel length (e.g. less than about 4 .mu.m) less than the feature size of the lithography used so as to maximize I.sub.ON /C.sub.gs(ON) of the TFT. Maximizing I.sub.ON /C.sub.gs(ON) reduces pixel flickering, gray scale non-uniformity, and image retention in LCD applications.

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