Wafer level integrated circuit testing with a sacrificial metal

Details Wafer level integrated circuit testing with a sacrificial metal Wafer level integrated circuit testing with a sacrificial metal

1994-04-22

1996-07-02

Fourson, George

Fishing, trapping, and vermin destroying

437226, H01L 2166

Patent

active

055321747

ABSTRACT:
A method and structure for wafer level testing of integrated circuit dice. A plurality of conductive paths are formed from a sacrificial metal layer and routed through the scribing lanes of the wafer. These conductive paths extend from selected I/O pads of the integrated circuit dice to an other portion of the wafer. Multiplexing and testing circuitry may also be formed on the wafer to facilitate integrated circuit testing. The novel method of the present invention further includes the step of removing the conductive paths before the wafer is segmented or otherwise operationally used. In one embodiment the conductive paths are formed from a conductive material differing from the conductive material used to form the I/O pads of the integrated circuits. Etching or heating may then preferentially remove the conductive paths prior to segmenting or otherwise operationally using the wafer. In an alternative embodiment an etching resistant mask is deposited over upper surfaces of the integrated circuit dice prior to the etching step. This mask protects the I/O pads and portions of the conductive paths overlapping the I/O pads. After the conductive paths have been removed by etching, the mask is also removed. In this embodiment the conductive paths may be formed from the same conductive material as the integrated circuit I/O pads.

REFERENCES:
patent: 3761675 (1973-09-01), Mason et al.
patent: 3806891 (1974-04-01), Eichelberger et al.
patent: 3849872 (1974-11-01), Hubacher
patent: 3969670 (1976-07-01), Wu
patent: 4255672 (1981-03-01), Ohno et al.
patent: 4293919 (1981-10-01), Dasgupta et al.
patent: 4340857 (1982-07-01), Fasang
patent: 4423509 (1983-12-01), Feissel
patent: 4479088 (1984-10-01), Stopper
patent: 4511914 (1985-04-01), Remedi et al.
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4714876 (1987-12-01), Gay et al.
patent: 4749947 (1988-06-01), Gheewala
patent: 4789641 (1988-12-01), Inuzuka
patent: 4855253 (1989-08-01), Weber
patent: 4884118 (1989-11-01), Hui et al.
patent: 4937203 (1990-06-01), Eichelberger et al.
patent: 4937826 (1990-06-01), Gheewala et al.
patent: 4961053 (1990-10-01), Krug
patent: 4967146 (1990-10-01), Morgan et al.
patent: 4968931 (1990-11-01), Littlebury et al.
patent: 4975640 (1990-12-01), Lipp
patent: 4985988 (1991-01-01), Littlebury
patent: 5047711 (1991-09-01), Smith et al.
patent: 5053700 (1991-10-01), Parrish
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5081601 (1992-01-01), Eirikasson
patent: 5130644 (1992-07-01), Ott
patent: 5149662 (1992-09-01), Eichelberger
patent: 5159752 (1992-11-01), Mahant-Shetti et al.
patent: 5279975 (1994-01-01), Deveraux et al.
patent: 5289631 (1994-03-01), Koopman et al.
patent: 5307010 (1994-04-01), Chiu
patent: 5366906 (1994-11-01), Wojnarowski et al.
patent: 5399505 (1995-03-01), Dasse et al.

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