Method for forming aligned interconnections between logic stages

Details Method for forming aligned interconnections between logic stages Method for forming aligned interconnections between logic stages

1985-10-30

1988-05-03

Ozaki, George T.

Fishing, trapping, and vermin destroying

307445, 307448, 357 41, 437 52, 437195, 437 49, H01L 2138, H01L 2144

Patent

active

047420197

ABSTRACT:
A layout for random logic in which different stages are assigned to columns according to the flow of logic signal. Each stage may consist of several parallel logic blocks defining a logic function and having an output. The logic blocks are implemented by several diffusion areas, not necessarily contiguous. The output line of a logic block is aligned vertically to match one or more gate electrodes of following stages that it drives. The interconnection to the following stages can be implemented by a single horizontal polysilicon line which also functions as the gate electrodes. The breaks in the diffusion of a logic block can accommodate the passage of polysilicon lines not being used in that logic block.

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Cook et al. Polysilicon Gate MOSFETs for Weinberger-Type Random Logic Arrays, IBMTDB, vol. 19, No. 6, Nov. 1976, pp. 2303-2304.

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