Process for the manufacture of an integrated voltage limiter and

Details Process for the manufacture of an integrated voltage limiter and Process for the manufacture of an integrated voltage limiter and

1994-09-07

1996-01-23

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437149, 148DIG174, H01L 218247

Patent

active

054864860

ABSTRACT:
A process for the manufacture of an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well on a single-crystal silicon substrate; a step of formation of an active area on the surface of said N type well; a step of growth of a thin gate oxide layer over said active area; a step of implantation of a first heavy dose of N type dopant into said N type well to obtain an N type region; a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region to obtain an N+ contact region to both the N type well and said N type region; a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region to form a P+ region.

REFERENCES:
patent: 4473941 (1984-10-01), Turi et al.
patent: 5103425 (1992-04-01), Kuo et al.
patent: 5170232 (1992-12-01), Narita
patent: 5322803 (1994-06-01), Cappelletti et al.

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