Method of fabricating an isolation region for a semiconductor de

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437238, H01L 2176

Patent

active

055610765

ABSTRACT:
The invention provides a method of fabricating a semiconductor device on an SOI substrate having a single crystal silicon substrate, a silicon dioxide film laid on top of the silicon substrate and a single crystal silicon layer laid on top of the silicon dioxide film. The method includes the steps of forming a single crystal silicon island composed of the single crystal silicon layer in a first region in which the semiconductor device is to be fabricated, and selectively forming a low temperature deposition silicon dioxide film in a second region in which the semiconductor device is not to be fabricated in the presence of photoresist, so that the low temperature deposition silicon dioxide film covers side surfaces of the silicon island. The second region turns into an isolation region for electrically separating adjacent semiconductor devices.

REFERENCES:
patent: 4468420 (1984-08-01), Kawahara et al.
patent: 4596071 (1986-06-01), Kita
patent: 4851078 (1989-07-01), Short et al.
patent: 4916086 (1990-04-01), Takahashi
patent: 4927781 (1990-05-01), Miller
patent: 5024965 (1991-06-01), Chang et al.
patent: 5036021 (1991-07-01), Goto
patent: 5196373 (1993-03-01), Beasom
patent: 5453395 (1995-09-01), Lar
patent: 5472902 (1995-12-01), Lar
Vasudev, P. K., et al., "A High Performance Submicrometer CMOS/SOI Technology Using Ultrathin Silicon Films on SIMOX," 1988 Symposium on VLSI Technology Digest of Technical Papers, May 10-13, 1988, pp. 61-62.
Homma, T, et al, "A Selective SiO.sub.2 Film-Formation . . . Multilevel Interconnections", J. Electrochem. Soc., vol. 140, No. 8, Aug. 1993.
Omura, Y., et al., "A 4kb CMOS/SIMOX SRAM," 1985 Symposium on VLSI Technology Digest of Technical Papers, May 14-16, 1985, pp. 24-25.
Vogt, H., et al., "MESFETs in Thin Silicon on SIMOX," Electronics Letters, vol. 25, No. 23, Nov. 9, 1989, pp. 1580-1581.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of fabricating an isolation region for a semiconductor de does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating an isolation region for a semiconductor de, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating an isolation region for a semiconductor de will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1501738

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.