Error reporting scheme

Details Error reporting scheme Error reporting scheme

Filed on

1981-07-30

Date issued

1984-06-05

Examiner

Smith, Jerry

Patent Class

Boots, shoes, and leggings

Other Related Categories

371 16, G06F 1100

Type

Patent

Status

active

Patent number

044532130

Description

ABSTRACT:
Errors occurring during data communications in a data processor communication network are routed by way of an arbitration module to a maintenance and processor. In the event of an error, the module which detects the error immediately terminates its present operation and, after gaining access to the communication bus, reports the error to the arbiter. In so doing, the error reporting module sets an error bit on an error signal line that forms part of the command bus. When the arbiter sees the error bit line set, it ignores the destination address produced by the logical-physical address table which identifies the other participant (destination module) in the transfer in which the error arose, and, instead, substitutes the physical address of the maintenance processor as the intended recipient of the transfer. When the maintenance processor sees it physical address line set, it can proceed to analyze the error report. Since the identities of the source and destination addresses of the participants in the transfer in which the error arose are defined by the contents of the source and destination portions of the address bus, the maintenance processor merely needs to read these buses to learn the location of each module participating in the error transfer.

REFERENCES:
patent: 3921141 (1975-11-01), Wilber et al.
patent: 4228496 (1980-10-01), Katzman et al.
patent: 4262357 (1981-04-01), Shima
patent: 4263649 (1981-04-01), Lapp
patent: 4320452 (1982-03-01), Kempf et al.
patent: 4374414 (1983-02-01), Comfort et al.

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