Processor having multiple instruction registers

Details Processor having multiple instruction registers Processor having multiple instruction registers

1994-11-23

1997-07-15

Coleman, Eric

Boots, shoes, and leggings

395376, 364DIG1, G06F 938

Patent

active

056492260

ABSTRACT:
A program is stored alternately in the memories 1A and 1B one word at a time. One execution circuit 5 is induced to select and execute the outputs of instruction decoders 4A and 4B alternately. After the execution circuit 5 holds the output of the instruction decoder 4A (4B), the instruction decoder 4A (4B) is induced to decode the output of the instruction register 3A (3B), a program counter 2A (2B) is induced to update the output and a instruction register 3A (3B) is induced to hold the output of the memory 1A (1B).

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patent: 5283874 (1994-02-01), Hammond
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patent: 5381531 (1995-01-01), Hanawa
patent: 5559975 (1996-09-01), Christie
patent: 5561775 (1996-10-01), Kurosawa
patent: 5574937 (1996-11-01), Narain

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