Processor structure and method for maintaining and restoring pre

Details Processor structure and method for maintaining and restoring pre Processor structure and method for maintaining and restoring pre

1995-06-07

1997-07-15

Treat, William M.

39518314, G06F 1100

Patent

active

056491360

ABSTRACT:
A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring precise state at any instruction boundary; (3) tracking instruction status to maintain precise state; (4) checkpointing instructions to maintain precise state; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state.

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Mike Johnson, Superscalar Microprocessor Design, 1991.

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