Patent
1994-06-17
1997-07-15
Harvey, Jack B.
395891, G06F 1300
Patent
active
056491247
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
a) Field of the Invention
The invention concerns a high-speed bus system and a method of operating the high-speed bus system using at least one parallel bus and at least one serial bus. Various types of bus system are known, including bus systems that have already been standardized such as the VMEbus, which conveniently has two idle lines which are not used for connection setup or for parallel data transfer (SERDAT and SERCLK).
b) Background Art
The standard parallel VMEbus is described in the publication entitled "The VMEbus Specification" in accordance with ANSI/IEEE STD1014-1987, IEC821 and 297 of the VMEbus International Trade Association, 10229 N. Scottsdale Road, Suite E, Scottsdale, Ariz. 85253, U.S.A., (602) 951-8866.
So-called "message passing" in parallel bus systems is a known method of implementing fast data transfer. However, this known method has serious drawbacks because the parallel bus is occupied during the time required for data transfer and this known method is considerably expensive in terms of hardware.
The task which the invention aims to solve is to create a high-speed bus system which allows a significant increase in the speed of data transfer, in particularly even where conventional bus systems are used, and which can be adapted to suit extremely different data transfer conditions. In addition, the invention is also intended to provide a method of operating such a high-speed bus system.
SUMMARY OF THE INVENTION
In order to solve this task, the present invention provides a high-speed bus system in which at least one parallel bus and at least one serial bus are combined for simultaneous parallel and serial data transfer with serial data transfer taking place after connection setup at the same time as normal transfer of data and/or programs takes place on the parallel bus and where connection setup for both parallel and serial data transfer takes place using the logic circuitry of the parallel bus.
The high-speed bus system according to this invention can, in particular, also be implemented fully in existing and/or standardized bus systems and ideally the parallel bus consists of a standard VMEbus, a standard Futurebus or a so-called Multibus II (a parallel system bus which consists of sixty four lines, each of which has a defined use, this being capable of having one or more of lines being converted to serial data transfer) and at least one of the lines of these standard buses that are not normally used forms a high-speed serial bus. In other words, according to the invention, the idle lines in these standard buses are used as high-speed serial buses. If such a bus system does not have any "idle lines" (lines that are not used for connection setup or for data transfer), these can be created simply as an add-on link.
The invention can also be advantageously arranged so that in the event of block transfer in accordance with a protocol, the parallel data transferred during connection setup contains all the necessary information for serial transfer such as the start address, block length etc. with block transfer taking place exclusively via the serial bus.
Particularly where several bus systems of several subscribers are used or connected together, a high-speed serial/parallel and parallel/serial converter can be inserted between a parallel bus and a serial bus.
This high-speed serial/parallel and parallel/serial converter according to the invention has two functional units; one functional unit consists of a prescaler, a voltage-controlled oscillator and a phase-locked loop and the other functional unit contains an internal control logic circuit which, among other things, generates a busy signal (BUSY) when the serial bus is occupied.
With the high-speed bus system according to this invention, if several subscribers are combined for a data exchange, each of the subscribers can conveniently be equipped with such a high-speed serial/parallel and parallel/serial converter. The internal control logic circuit in each of these converters is designed so that if
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patent: 4570220 (1986-02-01), Tetrick et al.
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patent: 4641263 (1987-02-01), Perlman et al.
patent: 4688171 (1987-08-01), Selim et al.
patent: 5134702 (1992-07-01), Charych et al.
Auve Glenn A.
Harvey Jack B.
Hughes Robert B.
PEP Modular Computers AG
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