I/O toggle test method using JTAG

Details I/O toggle test method using JTAG I/O toggle test method using JTAG

1996-02-06

1997-07-15

Beausoliel, Jr., Robert W.

Excavating

371 27, G01R 3128

Patent

active

056489730

ABSTRACT:
A method for toggling the output pins of a IC chip to satisfy an ASIC manufacturer's output toggle test requirements parallel loads data from an IC tester into the IC's JTAG boundary scan data shift register, so that the parallel loaded data is an alternating high and low data bits. The test pattern of alternating data bits is then latched to the JTAG data latch register and driven onto the output pins of the IC chip. The bidirectional buffers connected to the output pins are then enabled for output while the IC tester tri-states its alternating data test pattern. The test pattern is then shifted by one bit within the IC's JTAG shift register and parallel loaded into the JTAG latch register on the next clock cycle. In this manner, the complement of a test pattern driven onto the output pins by the external test circuit is driven out from the IC chip. The process is then repeated once more to provide an alternating transition for each of the output pins so that a toggle from high to low and also from low to high is satisfied for each of the output pins on the IC chip.

REFERENCES:
patent: 5056094 (1991-10-01), Whetsel
patent: 5150366 (1992-09-01), Bardell, Jr. et al.
patent: 5253255 (1993-10-01), Carbine
patent: 5416784 (1995-05-01), Johnson
patent: 5495487 (1996-02-01), Whetsel, Jr.
"IEEE Standard Test Access Port and Boundary-Scan Architecture", Circuits and Devices Communications Technology, IEEE Std 11.49.1-1990 (includes IEEE Std 1149.1A-1993), Oct. 21, 1993.

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