Semiconductor memory system with programmable address decoder

Details Semiconductor memory system with programmable address decoder Semiconductor memory system with programmable address decoder

1986-09-25

1990-01-09

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518905, 3652335, G11C 700, G11C 800

Patent

active

048932817

ABSTRACT:
A semiconductor memory system using address signals each consisting of a first predetermined number of logic bits, comprising a memory array having a number of memory cells and access lines along which the memory cells are arranged in rows or columns, and a programmable address decoder responsive to a second number of logic bits of each of the address signals, the second predetermined number being not larger than the first predetermined number. The address decoder comprises a plurality of address generation networks commonly connected to the address bus and respectively associated with the access lines and is operative to generate a predetermined sequence of address bits representing a desired address for one of the access lines in the memory array in response to the second predetermined number of address bits of each of the address signals. Each of the address generation networks comprises a plurality of programmable memory cells and a switching circuit for selecting memory cells out of all the programmable memory cells of each of the address generation networks in response to the predetermined sequence of the address bits generated in the address decoder.

REFERENCES:
patent: 4441167 (1984-04-01), Principi
patent: 4633429 (1986-12-01), Lewandowsk et al.

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