Multiple native instruction set master/slave processor arrangeme

Details Multiple native instruction set master/slave processor arrangeme Multiple native instruction set master/slave processor arrangeme

1996-11-27

2000-07-04

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing architecture

Distributed processing system

712 1, 712 28, 712 29, 712 30, 712 33, 712 34, 712200, 712209, 39550001, 39550002, 3955004, 39550047, 39550049, G06F 1516

Patent

active

060853077

ABSTRACT:
A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as a slave processor in the aforementioned master/slave multi-processor computer system the slave processor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is in effect native to the slave processor.

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