Logic control system including cache memory for CPU-memory trans

Details Logic control system including cache memory for CPU-memory trans Logic control system including cache memory for CPU-memory trans

1981-09-16

1984-07-17

Smith, Jerry

Boots, shoes, and leggings

G06F 1300

Patent

active

044609590

ABSTRACT:
A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.

REFERENCES:
patent: 4135242 (1979-01-01), Ward et al.
patent: 4246644 (1981-01-01), Flynn et al.
patent: 4312036 (1982-01-01), Porter et al.
patent: 4319324 (1982-03-01), Johnson et al.
patent: 4322795 (1982-03-01), Lange et al.
patent: 4348724 (1982-09-01), Cushing et al.
patent: 4360869 (1982-11-01), Stanley et al.
patent: 4382278 (1983-05-01), Appelt

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