Interruption control method for multiprocessor system

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G06F 946, G06F 1516

Patent

active

042689040

ABSTRACT:
An interrupt control method for a multiprocessor system including a plurality of microprocessors wherein sections of a main memory, which is shared among the processors of the system, are allocated to store entry address data pointing to a plurality of interrupt-servicing programs for each of the several processors of the system. Interrupt commands are coded to designate different interrupt levels which are compared against mask flag bits and a master mask flag bit unique to each processor to determine which processor will respond to the interrupt command. The processors are arranged in a fixed priority sequence and respond to an interrupt command in a designated priority order. Controls are provided to prevent a processor which is executing an interrupt-servicing program from responding to a subsequent interrupt command until execution of the interrupt-servicing program is completed.

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