Semiconductor integrated circuit device with low power consumpti

Details Semiconductor integrated circuit device with low power consumpti Semiconductor integrated circuit device with low power consumpti

1981-05-06

1984-07-17

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307291, 307577, 307304, H03L 500, H03K 17693

Patent

active

044608357

ABSTRACT:
A mode switching transistor which is controlled by a chip enable signal is connected between a power supply terminal and a MOS inverter including transistors. The transistor functions as a weak depletion or depletion type MOS transistor to provide sufficient current with a first back gate bias given in an active mode and functions as a perfect enhancement type transistor to completely cut off current with a second back gate bias given in a standby mode.

REFERENCES:
patent: 3660827 (1972-05-01), Tickle
patent: 4092548 (1978-05-01), Beilstein, Jr. et al.
patent: 4096584 (1978-06-01), Owen et al.
patent: 4103189 (1978-07-01), Perlegos et al.
patent: 4296340 (1981-10-01), Horan
De La Moneda et al., "Paralleling IGFET Loads for Improved Current Driving", IBM Tech. Disc. Bull., vol. 22, No. 1, 6-79, pp. 220-222.
IEEE Transactions on Nuclear Science, No. 6, Dec. 1979, E. E. King, "Radiation-Hardening Status NMOS RAMS", pp. 5060-5064.
Electronics, vol. 50, No. 16, Aug. 4, 1977, R. Pashley et al. "Speedy RAM Runs Cool With Power-Down Circuitry" pp. 103 to 107.
Patent Abstracts of Japan, vol. 2, No. 153, Dec. 22, 1978, Kokai No. 53-121562 issued to Masouka.
Patent Abstracts of Japan, vol. 2, No. 153, Dec. 22, 1978, p. 9854E78, Kokai No. 53-121561 issued to Tarui.

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