Synchronous semiconductor memory device and bus control method

Details Synchronous semiconductor memory device and bus control method Synchronous semiconductor memory device and bus control method

1999-06-02

2000-07-04

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 36523008, 36518904, 36518905, G11C 800

Patent

active

060848235

ABSTRACT:
There is provided a semiconductor integrated circuit memory comprising banks each having at least one memory cell array and connected to a first data bus. Each of the banks includes a control part which is supplied with information indicated by a command and thus controls a data write or read operation on a corresponding bank. The control part controls data write and read operations on the corresponding bank so that the corresponding bank is prevented from occupying the first data bus until read data is output to the first data bus by the data read operation.

REFERENCES:
patent: 4564926 (1986-01-01), Nikaido et al.
patent: 4928265 (1990-05-01), Higuchi et al.
patent: 5835443 (1998-11-01), Fujita
"A Multimedia 32b RISC Microprocessor with 16 Mb DRAM", IEEE ISSCC'96, Session 13 Microprocessors Paper, FP13.4, p. 178.
"An Access-Sequence Control Scheme to Enhance Random Access Performance of Embedded DRAMs", Ayukawa et al, 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 59-60.
"A Modular Architecture for a 6.4-Gbyte/s, 8-Mbit Media Chip", Watanabe et al., 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 42-43 .

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