Memory including master and local word lines coupled to memory c

Details Memory including master and local word lines coupled to memory c Memory including master and local word lines coupled to memory c

1995-06-07

1998-03-10

Swann, Tod R.

Boots, shoes, and leggings

364DIG1, 36424612, 365 49, 365 51, 365 63, 36523006, 395403, 395463, 395470, 395451, 395457, 395750, G06F 1200, G06F 1300, G11C 700, G11C 800

Patent

active

057271801

ABSTRACT:
An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/least recently used (LRU) cache write mode. The cache stores TAG, index and LRU information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. The master word lines and local word lines having approximately the same cycle time. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The architecture circuitry efficiently updates the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.

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