Voltage level shifting circuit

Details Voltage level shifting circuit Voltage level shifting circuit

1997-10-17

2000-07-04

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327219, 326 68, 326 81, H03L 500

Patent

active

060844590

ABSTRACT:
An improved voltage level shifting circuit which is capable of increasing a level shifting speed and reducing a current consumption and layout area by decreasing a pull-up capacity of the pull-up PMOS transistors in a side in which a voltage level is shifted to a low level and increasing a pull-up capacity through the NMOS transistors in a side in which a voltage level is shifted to a high level. The voltage level shifting circuit includes a pull-up PMOS transistor and a pull-down NMOS transistor connected in series between a voltage Vpp terminal and a voltage Vss terminal and having a common drain which acts a first voltage terminal, a pull-up PMOS transistor and a pull-down NMOS transistor connected in series between the voltage Vpp terminal and the voltage Vss terminal, configured symmetrically with respect to the pull-up PMOS transistor and pull-down NMOS transistor, and having a common drain which acts as a second voltage terminal, a first conductive type MOS transistor a source of which is connected with a gate of the pull-up PMOS transistor and the second voltage terminal, respectively and a gate of which is connected with an input terminal, and a second conductive type MOS transistor a source of which is connected with a gate of the pull-up PMOS transistor and the first voltage terminal, respectively, and a gate of which is connected with the input terminal through an inverter.

REFERENCES:
patent: 4695744 (1987-09-01), Giordano
patent: 4845381 (1989-07-01), Cuevas
patent: 5698993 (1997-12-01), Chow

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