Toggle bus circuit

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Details

395312, G06F 1300

Patent

active

057271739

ABSTRACT:
A bus transceiver system transfers data among a plurality (N) of system components. The system includes N toggle bus transceiver circuits (TBT.sub.i, for i=0 through N-1), each of which corresponds to a respective one of the system components. Each toggle bus transceiver circuit has bi-directional driver circuitry which has M first terminals (D.sub.i,j, for j=0 through M-1). Each of the M first terminals are coupled to a respective bit of the system component to which that toggle bus transceiver circuit corresponds. Each toggle bus tranceiver circuit further has M second terminals (P.sub.i,j). Driver switch circuitry of each toggle bus transceiver circuit selectively connects each of the M first terminals to at least one of said M second terminals. In a first mode, the driver circuitry drives in a first direction and in a second mode, the driver circuitry drives in a second direction. Repeater of each toggle bus transceiver circuit has M third terminals (Q.sub.i,j) and M latch circuits (L.sub.i,j). Repeater switch circuitry selectively connects each of the M third terminals to at least one of the latch circuits. In the first mode, each latch circuit latches a data signal provided at the third terminal to which the latch circuit is connected, and in the second mode, the latch circuit provides a data signal latched by the latch circuit to the third terminal to which said latch circuit is connected. A permuted interconnect network couples the second terminals of the toggle bus transceiver circuit bi-directional driver circuitry to the third terminals of the toggle bus transceiver circuit repeater circuitry for permuted signal transfer therebetween.

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Howard Jay Siegel and William Tsun-yuk Hsu (Ed. Veljko M. Milutinovic), "Computer Architecture: Concepts and Systems," North-Holland, 1988.

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