Microinstruction controlled data processor

Details Microinstruction controlled data processor Microinstruction controlled data processor

1982-11-26

1985-01-15

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 926

Patent

active

044941951

ABSTRACT:
Herein disclosed is a microinstruction controlled data processor in which a microinstruction memory (i.e., an ROM) is driven in each predetermined cycle thereby to generate a plurality of microinstructions in accordance with a page address it receives and in which a general microinstruction contains the page address and the displacement address of the plural preceding microinstructions. One of the plural instructions read out of the ROM is selected upon each read-out operation. The page and displacement addresses in the microinstruction thus selected are set in an address register at the timings for reading out the plural microinstructions. Moreover, a displacement address generator for selecting the plural microinstructions read out of the ROM generates the displacement addresses which are different in dependence upon whether a branch instruction exists in the instructions selected during the same number of cycles as that of the plurality or not and whether the branching operation succeeds or not in case the branch instruction exists.

REFERENCES:
patent: 4338661 (1982-07-01), Tredennick et al.

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